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[Other resource] clockbyvhdl

Description: 在xilinx的ise环境下用vhdl编写的一个时钟程序。-in the environment and ideally with the preparation of a VHDL clock procedures.
Platform: | Size: 27680 | Author: 马永涛 | Hits:

[Other resource] ClockDiv

Description: 本程序以XILINX公司的ISE８.２为开发平台，采用VHDL为开发语言，实现了对一个时钟信号分频的功能-the procedures to XILINX ISE8.2 for the development platform VHDL used for the development of language, the right to achieve a clock frequency of the signal function
Platform: | Size: 774440 | Author: 刘小军 | Hits:

[VHDL-FPGA-Verilog] clockbyvhdl

Description: 在xilinx的ise环境下用vhdl编写的一个时钟程序。-in the environment and ideally with the preparation of a VHDL clock procedures.
Platform: | Size: 27648 | Author: 马永涛 | Hits:

[Technology Management] 06626_DLL

Description: XILINX的DLL的使用介绍，对于时钟的应用有很大的帮助-XILINX the use of the DLL, the application for the clock will be very helpful
Platform: | Size: 1009664 | Author: fei0318 | Hits:

[VHDL-FPGA-Verilog] ClockDiv

Description: 本程序以XILINX公司的ISE８.２为开发平台，采用VHDL为开发语言，实现了对一个时钟信号分频的功能-the procedures to XILINX ISE8.2 for the development platform VHDL used for the development of language, the right to achieve a clock frequency of the signal function
Platform: | Size: 774144 | Author: 刘小军 | Hits:

[Other] hdb3_proc

Description: HDB3编解码，含时钟提取，极高的效率和可靠性，VHDL。-HDB3 coding and decoding, including clock extraction, high efficiency and reliability, VHDL.
Platform: | Size: 4096 | Author: BrivaMa | Hits:

[VHDL-FPGA-Verilog] clock

Description: 自己编写的一个verilog时钟程序，在xilinx的ISE仿真通过-I have written a Verilog clock procedures, in Xilinx s ISE simulation through
Platform: | Size: 327680 | Author: lg | Hits:

[VHDL-FPGA-Verilog] eternityclock

Description: 一个在Xilinx spartan3实现的时钟，具有时分秒的计时显示以及年月日的显示，很有参考价值-A Xilinx spartan3 realize the clock, with time-accurate time display and date display, a good reference
Platform: | Size: 773120 | Author: Roger | Hits:

[MPI] v2_fifo_vhd_258

Description: 这是一个基于xilinx ISE9.1的一个历程，包含两个FIFO代码，第一个FIFO读写用同一个时钟，第二个FIFO读写用不同的时钟。-This is a xilinx ISE9.1 based on a course code consists of two FIFO, the first FIFO read and write using the same clock, the second FIFO read and write with a different clock.
Platform: | Size: 92160 | Author: muerqing | Hits:

[Com Port] uart

Description: 串口通讯rs232,时钟频率为40Mhz,波特率为19200,没有奇偶校验,在xilinx XC3S200A板子上验证过.-Serial communication rs232, clock frequency of 40Mhz, the baud rate to 19200, no parity, in the board on xilinx XC3S200A verified.
Platform: | Size: 6144 | Author: zhangjiansen | Hits:

[VHDL-FPGA-Verilog] clock_module_ref

Description: Xilinx clock module design
Platform: | Size: 2048 | Author: Mingli | Hits:

[VHDL-FPGA-Verilog] oc_mkjpeg

Description: Pure hardware JPEG Encoder design. Package includes vhdl source code, test bench, detail design document. Written in VHDL. Verified on Xilinx XC4VLX25. Rncode 320x240 bmp picture in 3ms at 50 quality, 100Mhz clock.-Pure hardware JPEG Encoder design. Package includes vhdl source code, test bench, detail design document. Written in VHDL. Verified on Xilinx XC4VLX25. Rncode 320x240 bmp picture in 3ms at 50 quality, 100Mhz clock.
Platform: | Size: 3267584 | Author: Andy | Hits:

[VHDL-FPGA-Verilog] clock_generator_0_wrapper

Description: 赛灵思FPGA开发板上时钟源的VHDL源代码，可作为硬件设计参考资料！-Xilinx FPGA development board clock source of the VHDL source code, hardware design can be used as reference!
Platform: | Size: 2048 | Author: dc | Hits:

[source in ebook] sanfenpin

Description: verilog 三分频 分频器是FPGA设计中使用频率非常高的基本设计之一，尽管在目前大部分设计中，广泛使用芯片厂家集成的锁相环资源，如altera 的PLL，Xilinx的DLL.来进行时钟的分频，倍频以及相移。-verilog-third of the frequency divider is a FPGA design, very high frequency of use, one of the basic design, although most of the designs in the current widespread use of factory-integrated PLL chip resources, such as altera of the PLL, Xilinx' s DLL. to for the sub-clock frequency multiplier and phase shift.
Platform: | Size: 1024 | Author: 杨化冰 | Hits:

[Documents] DDRIO

Description: Xilinx公司开发板中的一个模块，在时钟的上升和下降沿同时传输数据。使用时需要在ISE集成开发环境下利用VHDL进行例化。本文是对该模块功能的说明，是个人的学习总结-Xilinx has developed a module board, in the clock' s rising and falling at the same time transmission of data. ISE needs to use integrated development environment for the use of VHDL-based cases. This article is a description of the module function is to sum up the individual learning
Platform: | Size: 224256 | Author: 张潘睿 | Hits:

[VHDL-FPGA-Verilog] wtut_edif

Description: Xilinx clock. DIGITAL CLOCK for Spartan-3 Starter Board. This design shows how to generate a digital clock and display the output to the multiplexed 7- segment display in VHDL.
Platform: | Size: 20480 | Author: shad | Hits:

[VHDL-FPGA-Verilog] Xilinx_DCM

Description: 基于ise 10.0来实现Xilinx的时钟设计和管理-Xilinx dcm digital clock manager
Platform: | Size: 8192 | Author: ise_dcm | Hits:

[VHDL-FPGA-Verilog] clock

Description: XPS做时钟的配置过程基于EXCD-1开发板,其实是基于xilinx的ISE来开发的，但是开发环境没有这个就这能选VHDL，另外是verilog的，呵呵。希望大家能够真正用上，挺好的“基于ISE的时钟”-XPS to do the configuration process is based on the clock EXCD-1 development board, in fact, is based on the xilinx the ISE to develop, but not the development environment that can be selected to VHDL, the other is verilog, huh, huh. Hope that we can really spend, very good " based on ISE' s Clock"
Platform: | Size: 2779136 | Author: 江源 | Hits:

[SCM] adfmreceiver

Description: The design of the All Digital FM Receiver circuit in this project uses Phase Locked Loop (PLL) as the main core. The task of the PLL is to maintain coherence between the input (modulated) signal frequency,iωand the respective output frequency,oωvia phase comparison. This self-correcting ability of the system also allows the PLL to track the frequency changes of the input signal once it is locked. Frequency modulated input signal is assumed as a series of numerical values (digital signal) via 8-bit of analog to digital conversion (ADC) circuit. The FM Receiver gets the 8 bit signal every clock cycle and outputs the demodulated signal. The All Digital FM Receiver circuit is designed using VHDL, then simulated and synthesized using ModelSim SE 6 simulator and Xilinx ISE 6.3i, respectively. FPGA implementation also provided, here we use Virtex2 device.
Platform: | Size: 658432 | Author: vijay | Hits:

[VHDL-FPGA-Verilog] SIG_CLK

Description: 四分频，四个相位的时钟输出，FPGA，vhdl，xilinx-Divided by four, four-phase clock output, FPGA, vhdl, xilinx
Platform: | Size: 1024 | Author: lal | Hits:
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